Each complementary thin film transistor (CMOS TFT) comprises a first thin film transistor and a second thin film transistor, wherein, one of the thin film transistors is a P-type thin film transistor (PMOS TFT), and the other one of the thin film transistors is an N-type thin film transistor (NMOS TFT), thus various circuits and systems which are difficult to be achieved by PMOS TFT or NMOS TFT may be achieved by using CMOS TFT.
As shown in FIG. 1, the conventional manufacturing method of CMOS TFT specifically comprises following steps 1 through 6.
Step 1, forming a pattern of a gate metal layer comprising a gate 21 of the first thin film transistor and a gate 22 of the second thin film transistor on a base 1, and the gate 21 of the first thin film transistor and the gate 22 of the second thin film transistor are electrically connected together.
Step 2, forming a gate insulation layer 3 on the base 1 subjected to the above step.
Step 3, forming a pattern of an active layer 4 of the first thin film transistor on the base 1 subjected to the above steps.
Step 4, forming a pattern of an active layer 5 of the second thin film transistor on the base 1 subjected to the above steps.
Step 5, forming an etching stop layer 6 on the base 1 subjected to the above steps, and etching the etching stop layer 6 to form source and drain contact regions for making a source 71, a drain 72 of the first thin film transistor and a source 81, a drain 82 of the second thin film transistor contact active regions thereof respectively.
Step 6, forming a pattern of a source and drain metal layer comprising the source 71, the drain 72 of the first thin film transistor and the source 81, the drain 82 of the second thin film transistor on the base 1 subjected to the above steps, wherein the drain 72 of the first thin film transistor and the source 81 of the second thin film transistor are adjacent to each other and electrically connected with each other.
As an example, the above steps are described for manufacturing the first and second thin film transistors of bottom gate type. The difference between the method for manufacturing the first and second thin film transistors of top gate type and the above method is mainly in that: first preparing an active layer and then manufacturing a gate, which will not be described in detail here.
The inventors of the present invention found that, there are at least following problems in the prior art: after preparing the active layer 4 of the first thin film transistor, when manufacturing the active layer 5 of the second thin film transistor, since the material of the active layer 4 of the first thin film transistor is different from the material of the active layer 5 of the second thin film transistor, the deposited material of the active layer 4 of the first thin film transistor may be affected, specifically, the film of the active layer of the second thin film transistor, which is deposited after forming the active layer 4 of the first thin film transistor, may contact the active layer 4 of the first thin film transistor, even if the film of the active layer of the second thin film transistor above the active layer 4 of the first thin film transistor will be etched off in a subsequent process, it still will affect performance of the active layer 4 of the first thin film transistor, meanwhile, processing for the active layer 5 of the second thin film transistor will also affect the performance of the active layer 4 of the first thin film transistor, for example, plasma processing for the active layer 5 of the second thin film transistor may result in plasma bombardment damage of the active layer 4 of the first thin film transistor, in addition, processes such as high energy process (e.g., doping modification) and annealing in different atmospheres may also affect the performance of CMOS TFT, which results in deterioration of properties of CMOS TFT, for example, threshold voltage, subthreshold swing, stability, etc. of CMOS TFT may be deteriorated.